dcmpuq

Decimal Compare Unordered Quad-Precision

dcmpuq BF, vA, vB

Compares two 128-bit DFP numbers (Non-signaling).

Encoding

Binary Layout

63

0:5

BF

6:8

/

9:10

vA

11:15

vB

16:20

642

21:30

/

31

 

Format X-form

Opcode 0xFC000504

Extension Decimal Floating-Point

Operands

• BF
  CR Field
• vA
  Src A
• vB
  Src B

Example

dcmpuq cr0, va, vb

Registers Altered

FPSCR

Related

More in Decimal Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Compares two 128-bit Decimal Floating-Point values in vA and vB without signaling an exception on QNaN operands (unordered comparison). The result is written to the condition register field BF as: LT, GT, EQ, or UN (unordered). NaN comparisons result in UN, and FPSCR[VXSNAN] is not set unless SNaN is present.

Operation

if vA is NaN or vB is NaN then
  CR[BF] ← 0b0001 (UN)
else if vA < vB then
  CR[BF] ← 0b1000 (LT)
else if vA > vB then
  CR[BF] ← 0b0100 (GT)
else
  CR[BF] ← 0b0010 (EQ)

Programming Note

Use dcmpuq for comparing two DFP operands while handling unordered cases, which include NaNs. Ensure that the operands are properly aligned and check the FPSCR for exception conditions after execution.