dcmpoq

Decimal Compare Ordered Quad-Precision

dcmpoq BF, vA, vB

Compares two DFP values and sets the condition register based on their order.

Encoding

Binary Layout

0:5

6:8

9:10

11:15

16:20

130

21:30

Format X-form

Opcode 0xFC000104

Extension Decimal Floating-Point

Operands

BF
CR Field
vA
Src A
vB
Src B
RT
Target General Purpose Register
RA
Source General Purpose Register
RB
Source General Purpose Register

Example

dcmpoq cr0, va, vb

Registers Altered

CR0, FPSCR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Compares two 128-bit Decimal Floating-Point values in vA and vB with signaling behavior on NaN (ordered comparison). The result is written to the condition register field BF as: LT, GT, EQ, or UN (unordered). If either operand is QNaN, the VXSNAN exception is raised and FPSCR[VE] or FPSCR[FEX] handling applies; SNaN always signals VXSNAN.

Operation

if vA is SNaN or vB is SNaN then
  FPSCR[VXSNAN] ← 1
if vA is NaN or vB is NaN then
  CR[BF] ← 0b0001 (UN)
else if vA < vB then
  CR[BF] ← 0b1000 (LT)
else if vA > vB then
  CR[BF] ← 0b0100 (GT)
else
  CR[BF] ← 0b0010 (EQ)

Programming Note

The dcmpoq instruction is used to compare two quad-precision decimal floating-point numbers. It sets the CR0 register field to indicate whether the first operand is less than, greater than, or equal to the second operand. Ensure that operands are properly aligned and that the FPSCR (Floating Point Status and Control Register) is correctly configured for accurate comparison results.