vpkpx

Vector Pack Pixel

vpkpx vD, vA, vB

Packs the contents of two vector registers into a single vector register, with each source word being considered as a 32-bit pixel and each target halfword as a 16-bit pixel.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

782

21:31

Format VX-form

Opcode 0x1000030E

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vpkpx vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vpkpx, the contents of VSR[VRA+32] and VSR[VRB+32] are concatenated to form a single vector. Each word element from this concatenated vector is then packed into a halfword element in VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
let vsrc be the concatenation of the contents of VSR[VRA+32] followed by the contents of VSR[VRB+32].
do i = 0 to 7
    VSR[VRT+32].hword[i].bit[0] ← vsrc.word[i].bit[7]
    VSR[VRT+32].hword[i].bit[1:5] ← vsrc.word[i].bit[8:12]
    VSR[VRT+32].hword[i].bit[6:10] ← vsrc.word[i].bit[16:20]
    VSR[VRT+32].hword[i].bit[11:15] ← vsrc.word[i].bit[24:28]

Programming Note

Each source word can be considered to be a 32-bit 'pixel', consisting of four 8-bit 'channels'. Each target halfword can be considered to be a 16-bit pixel, consisting of one 1-bit channel and three 5-bit channels.