xssqrtdp

VSX Scalar Square Root Double-Precision

xssqrtdp XT, XB

Computes the unbounded-precision square root of a double-precision floating-point value and rounds it to double-precision format.

Encoding

Binary Layout

11110001

00000000

1000

Format XX2-form

Opcode 0xF000012C

Extension VSX

Operands

XT
Target
XB
Source
VX
Target Vector Register
VB
Source Vector Register

Example

xssqrtdp vs1, vs3

Registers Altered

FPSCR (FPRF, FR, FI, FX, XX), VXSNAN, VXSQRT

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction computes the square root of the double-precision floating-point value in doubleword element 0 of VSR[XB]. The result is placed into doubleword element 0 of VSR[XT] in double-precision format, with doubleword element 1 set to 0. The FPRF is updated to reflect the class and sign of the result, and FR and FI are set based on rounding operations.

Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ← bfp_SQUARE_ROOT(src)
rnd ← bfp_ROUND_TO_BFP64(0b0, FPSCR.RN, v)
result ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)
if xx_flag=1 then SetFX(FPSCR.XX)
vx_flag ← vxsnan_flag | vxsqrt_flag
vex_flag ← FPSCR.VE & vx_flag
if vex_flag=0 then do
    VSR[32×TX+T].dword[0] ← result
    VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP64(result)
    FPSCR.FR ← inc_flag
    FPSCR.FI ← xx_flag
end else do
    FPSCR.FR ← 0b0
    FPSCR.FI ← 0b0
end

Programming Note

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.