xvcvbf16spn

VSX Vector Convert bfloat16 to Single-Precision format Non-signaling

xvcvbf16spn XT,XB

Converts a vector of bfloat16 values to single-precision floating-point format.

Encoding

Binary Layout

T

6:10

BX

11:15

TX

16:31

 

Format XX2-form

Opcode 0xF010076C

Extension VSX

Operands

• XT
  Target Vector Register
• XB
  Source Vector Register

Example

xvcvbf16spn vs1, vs3

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Converts each bfloat16 value in the source VSR to single-precision (32-bit) floating-point format and stores the results in the target VSR. This is a non-signaling variant that does not raise exceptions for invalid operations. The instruction operates on two elements per 128-bit register in VSX mode.

Operation

XT[0:31] ← ConvertBF16toSP(XB[0:15])
XT[32:63] ← ConvertBF16toSP(XB[16:31])
XT[64:95] ← ConvertBF16toSP(XB[32:47])
XT[96:127] ← ConvertBF16toSP(XB[48:63])

Programming Note

This instruction is used to convert bfloat16 values in a vector to single-precision floating-point format. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the MSR.VSX bit. The operation processes four elements per iteration, converting the high 16 bits of each source element to the corresponding target element while zeroing out the lower 16 bits. This instruction does not raise exceptions for invalid operations.