xvaddsp

VSX Vector Add Single-Precision

xvaddsp XT, XA, XB

Adds the contents of two single-precision floating-point vector registers and places the result in another vector register.

Details

For xvaddsp, each element of the source vector VSRA is added to the corresponding element of the source vector VSRC, and the results are placed into the destination vector VSRD.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0
do i = 0 to 3
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])
    src2 ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])
    v    ←bfp_ADD(src1,src2)
    rnd  ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)
    vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)

    if vxisi_flag=1 then SetFX(FPSCR.VXISI)
    if ox_flag=1 then SetFX(FPSCR.OX)
    if ux_flag=1 then SetFX(FPSCR.UX)
    if xx_flag=1 then SetFX(FPSCR.XX)

    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxisi_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.XE & xx_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

Programming Note

The xvaddsp instruction is used for adding single-precision floating-point numbers in vector registers. Ensure that the VSX feature is enabled by checking and setting MSR.VSX. Be aware of potential exceptions such as invalid operations (VXISI), overflow (OX), underflow (UX), or inexact results (XX). These conditions can be checked using the FPSCR flags.

Example

xvaddsp vs1, vs2, vs3

Encoding

Binary Layout
60
0
XT
6
XA
11
XB
16
64
21
 
Format XX3-form
Opcode 0xF0000040
Extension VSX
Registers Altered VSR, vxsnan_flag, vxisi_flag

Operands

  • XT
    Target
  • XA
    Src A
  • XB
    Src B
  • VSRD
    Destination Vector-Single-Precision Register
  • VSRA
    Source Vector-Single-Precision Register
  • VSRC
    Source Vector-Single-Precision Register