pmxvf32gernp

Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate

pmxvf32gernp AT,XA,XB,XMSK,YMSK

Performs a masked vector operation with negative multiplication and positive accumulation.

Details

The pmxvf32gernp instruction performs a masked vector operation where the result of multiplying two elements is added to an accumulator element. The operation is performed on single-precision floating-point values.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()

if 'xvf32ger' | 'xvf32gerpp' | 'xvf32gerpn' | 'xvf32gernp' | 'xvf32gernn' then do
    XMSK ←0b1111
    YMSK ←0b1111
end

do i = 0 to 3
    do j = 0 to 3
        if XMSK.bit[i]=1 & YMSK.bit[j]=1 then do
            reset_flags()

            src1 ←bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])
            src2 ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[j])
            acc  ←bfp_CONVERT_FROM_BFP32(ACC[AT][i].word[j])

            if '[pm]xvf32ger' then v ←bfp_MULTIPLY(src1, src2)
            if '[pm]xvf32gerpp' then v ←bfp_MULTIPLY_ADD(src1, src2, acc)
            if '[pm]xvf32gerpn' then v ←bfp_MULTIPLY_ADD(src1, src2, bfp_NEGATE(acc))
            if '[pm]xvf32gernp' then v ←bfp_MULTIPLY_ADD(src1, src2, bfp_NEGATE(acc))
            if '[pm]xvf32gernn' then v ←bfp_MULTIPLY_ADD(src1, src2, acc)

            r ←bfp_ROUND_TO_BFP32_DEFAULT(FPSCR.RN,v)

            if '[pm]xvf32gernp' then r ←bfp_NEGATE(r)
            if '[pm]xvf32gernn' then r ←bfp_NEGATE(r)

            ACC[AT][i].word[j] ←bfp32_CONVERT_FROM_BFP(r)

            if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
            if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
            if vxisi_flag=1 then SetFX(FPSCR.VXISI)
            if ox_flag=1 then SetFX(FPSCR.OX)
            if ux_flag=1 then SetFX(FPSCR.UX)
            if xx_flag=1 then SetFX(FPSCR.XX)
        end
        else
            ACC[AT][i].word[j] ←0x0000_0000
    end
end

Programming Note

This instruction is used for performing masked vector operations on single-precision floating-point values, specifically a GER (rank-1 update) operation with negative multiplication and positive accumulation. Ensure that the VSX feature is enabled in the MSR register to avoid exceptions. The instruction processes 4x4 elements, checking masks before performing operations. Be cautious of potential overflow or underflow conditions, as they can trigger exceptions and set flags in the FPSCR register.

Example

pmxvf32gernp acc0, vs2, vs3, 15, 15

Encoding

Binary Layout

XMSK

YMSK

Format MMIRR:XX3-form

Opcode

Extension VSX

Registers Altered FPSCR, VXSNAN, VXIMZ, VxisI, OX, UX, XX

Operands

AT
Target Accumulator Register
XA
Source Accumulator Register Index A
XB
Source Accumulator Register Index B
XMSK
Mask for Source Accumulator Register A
YMSK
Mask for Source Accumulator Register B