pmxvf32gernp

Prefixed Masked VSX Vector 32-bit Floating-Point GER (rank-1 update) Negative multiply, Positive accumulate

pmxvf32gernp AT,XA,XB,XMSK,YMSK

Performs a masked vector operation with negative multiplication and positive accumulation.

Encoding

Binary Layout

0:5

6:7

8:11

XMSK

12:13

YMSK

14:63

Format MMIRR:XX3-form

Opcode 0x07900000EC0002D0

Extension VSX

Operands

AT
Target Accumulator Register
XA
Source Accumulator Register Index A
XB
Source Accumulator Register Index B
XMSK
Mask for Source Accumulator Register A
YMSK
Mask for Source Accumulator Register B

Example

pmxvf32gernp acc0, vs2, vs3, 15, 15

Registers Altered

FPSCR, VXSNAN, VXIMZ, VxisI, OX, UX, XX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs a masked 4×4 generalized outer product (rank-1 update GER) on 32-bit floating-point elements, using negative multiplication and positive accumulation ('np' suffix). The XMSK and YMSK operands control which rows and columns participate in the operation. This is a prefixed VSX instruction requiring VSX and prefix support.

Operation

acc ← AT
for i in 0 to 3 do
  if XMSK[i] = 1 then
    for j in 0 to 3 do
      if YMSK[j] = 1 then
        a ← XA[i*32:(i+1)*32-1]
        b ← XB[j*32:(j+1)*32-1]
        prod ← -1.0 × a × b
        acc[i*32+j*8:(i*32+j*8+31)] ← acc[i*32+j*8:(i*32+j*8+31)] + prod
      end if
    end for
  end if
end for
AT ← acc

Programming Note

This instruction is used for performing masked vector operations on single-precision floating-point values, specifically a GER (rank-1 update) operation with negative multiplication and positive accumulation. Ensure that the VSX feature is enabled in the MSR register to avoid exceptions. The instruction processes 4x4 elements, checking masks before performing operations. Be cautious of potential overflow or underflow conditions, as they can trigger exceptions and set flags in the FPSCR register.