extswsli

Extend Sign Word and Shift Left Immediate

extswsli RA,RS,SH

Sign-extends the low-order 32 bits of a register, shifts it left by SH bits, and places the result in another register.

Encoding

Binary Layout

RS

6:10

RA

11:15

SH

16:20

445

21:29

Rc

30:31

 

Format XS-form

Opcode 0x7C0006F4

Extension Base

Operands

• RA
  Target General Purpose Register
• RS
  Source General Purpose Register
• SH
  Shift Amount (0-31)

Example

extswsli r4, r3, 3

Registers Altered

CR0

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of the low order 32 bits of RS are sign-extended to 64 bits and then shifted left SH bits. Bits shifted out of bit 0 are lost. Zeros are supplied to vacated bits on the right. The result is placed in register RA.

Operation

SH ← sh5 || sh0:4
r  ← ROTL64(EXTS64(RS32:63), SH)
m  ← MASK(0, 63-SH)
RA ← r & m

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.