divw

Divide Word

divw RT, RA, RB

Divides the contents of two registers and places the quotient into a target register.

Details

For divw, the 32-bit dividend is (RA)32:63. The 32-bit divisor is (RB)32:63. The 32-bit quotient is placed into RT32:63. The contents of RT0:31 are undefined.

Pseudocode Operation

if 'divw' then
    RT32:63 <- (RA)32:63 ÷ (RB)32:63
    RT0:31 <- undefined

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.

Example

divw r3, r4, r5

Encoding

Binary Layout
0
0
RT
6
RA
11
RB
16
OE
21
491
22
Rc
31
31
 
Format XO-form
Opcode 0x7C0003D6
Extension Base
Registers Altered CR0, XER

Operands

  • RT
    Target Register (Quotient)
  • RA
    Dividend
  • RB
    Divisor