divw

Divide Word

divw RT, RA, RB

Divides the contents of two registers and places the quotient into a target register.

Encoding

Binary Layout

31

0:5

RT

6:10

RA

11:15

RB

16:20

OE

21

491

22:30

Rc

31

 

Format XO-form

Opcode 0x7C0003D6

Extension Base

Operands

• RT
  Target Register (Quotient)
• RA
  Dividend
• RB
  Divisor

Example

divw r3, r4, r5

// r3 = r4 / r5 (32-bit Signed).

Registers Altered

CR0, XER

Related

Across architectures

Integer Divide : how x86, ARM, RISC-V, and PowerISA each do this.

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For divw, the 32-bit dividend is (RA)32:63. The 32-bit divisor is (RB)32:63. The 32-bit quotient is placed into RT32:63. The contents of RT0:31 are undefined.

Operation

if 'divw' then
    RT32:63 <- (RA)32:63 ÷ (RB)32:63
    RT0:31 <- undefined

Programming Note

When Rc=1 (dot form), CR0 is updated with the signed comparison of the result against zero (LT, GT, EQ) and the current SO bit from XER.