lbzci

Load Byte and Zero Caching Inhibited

lbzci RT, RA, RB

Loads a byte bypassing the cache. Used for memory-mapped I/O.

Details

Loads an unsigned byte from memory at address (RA + RB) with caching inhibited, zero-extending the result to 64 bits in RT. This instruction bypasses the cache hierarchy and is typically used for memory-mapped I/O operations. No condition registers are affected.

Pseudocode Operation

EA ← (RA) + (RB); RT ← 0x00000000000000ZZ where ZZ = [EA]

Example

lbzci r3, r4, r5

Encoding

Binary Layout
31
0
RT
6
RA
11
RB
16
854
21
/
31
 
Format X-form
Opcode 0x7C0006AC
Extension Base

Operands

  • RT
    Target
  • RA
    Base
  • RB
    Index