lbzci

Load Byte and Zero Caching Inhibited

lbzci RT, RA, RB

Loads a byte bypassing the cache. Used for memory-mapped I/O.

Details

The Load Byte and Zero Caching Inhibited instruction loads a byte bypassing the cache. Used for memory-mapped I/O.

Pseudocode Operation

r3 <- Memory[address]

Example

lbzci r3, r4, r5

Encoding

Binary Layout
31
0
RT
6
RA
11
RB
16
854
21
/
31
 
Format X-form
Opcode 0x7C0006AA
Extension Base

Operands

  • RT
    Target
  • RA
    Base
  • RB
    Index