vmulhsw

Vector Multiply High Signed Word

vmulhsw vD, vA, vB

Multiplies the signed integer values in each word element of two vector registers and places the high-order 32 bits of the 64-bit product into the corresponding word element of a third vector register.

Details

For vmulhsw, the signed integer value in word element i of VSR[VRA+32] is multiplied by the signed integer value in word element i of VSR[VRB+32]. The high-order 32 bits of the 64-bit product are placed into word element i of VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    src1 ←EXTS(VSR[VRA+32].word[i])
    src2 ←EXTS(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←CHOP32((src1 × src2) >> 32)
end

Programming Note

This instruction is used for multiplying signed integers stored in the high half of vector registers. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. The operation processes four 32-bit words per vector register, and the result is the high-order 32 bits of each 64-bit product. Be cautious with overflow conditions as they are not handled by this instruction.

Example

vmulhsw vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
904
 
Format VX-form
Opcode 0x10000388
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register