add

Add

add RT, RA, RB

Adds the contents of two registers and places the result in a third register.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

266

22:30

Format XO-form

Opcode 0x7C000214

Extension Base

Operands

RT
Target Register
RA
Source Register 1
RB
Source Register 2
rPX
Destination General Purpose Register
rPS
Source General Purpose Register
rNS
Source General Purpose Register

Example

add r3, r4, r5

// r3 = r4 + r5

Registers Altered

CR0, XER

Across architectures

Integer Addition : how x86, ARM, RISC-V, and PowerISA each do this.

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Adds the values in registers RA and RB and places the result in RT. If OE=1, sets XER[SO] and XER[OV] on signed overflow. If Rc=1, updates CR0 to reflect the result (LT, GT, EQ, SO). No exception is raised on overflow unless OE=1.

Operation

RT ← RA + RB
if OE = 1 then
  if overflow then XER[OV] ← 1; XER[SO] ← 1
if Rc = 1 then
  CR0 ← (RT < 0) || (RT > 0) || (RT = 0) || XER[SO]

Programming Note

add, add., and subf are the preferred instructions...

add

Add