xvi16ger2

VSX Vector Integer 16-bit GER (Rank-2 Update)

xvi16ger2 AT, XA, XB

Performs a rank-2 update of the contents of two registers and updates the condition register.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

21:28

AXBX

29:31

Format XX3-form

Opcode 0xEC000258

Extension MMA

Operands

AT
Accumulator
XA
Src A (16-bit)
XB
Src B (16-bit)

Example

xvi16ger2 acc0, vs2, vs3

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For xvi16ger2, the sum of the contents of register RA and RB is placed into register RT.

Operation

if MSR.VSX=0 then VSX_Unavailable()

PMSK ←0b11
XMSK ←0b1111
YMSK ←0b1111

do i = 0 to 3
   do j = 0 to 3
      if XMSK.bit[i] & YMSK.bit[j] then do
         prod0 ←(PMSK.bit[0]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].hword[0]) *
                                       EXTS(VSR[32×BX+B].word[j].hword[0])
         prod1 ←(PMSK.bit[1]=0) ? 0 : EXTS(VSR[32×AX+A].word[i].hword[1]) *
                                       EXTS(VSR[32×BX+B].word[j].hword[1])

         psum ←prod0 + prod1

         ACC[AT][i].word[j] ←CHOP32(psum)
      end
      else
         ACC[AT][i][j] ←0x0000_0000
   end
end

Programming Note

The xvi16ger2 instruction performs a 16-bit integer GER (Rank-2 Update) operation on VSX registers. Ensure that the VSX facility is enabled by checking and setting the MSR.VSX bit. The instruction processes 4x4 matrices of halfwords, multiplying corresponding elements and accumulating the results. Be cautious with overflow conditions as the products are summed without intermediate overflow checks. This instruction operates at the user privilege level and will raise an exception if VSX is unavailable.