vupkhsw

Vector Unpack High Signed Word

vupkhsw VRT,VRB

Unpacks the high signed words from a vector register into a doubleword format.

Details

Unpacks the two high-order signed 32-bit words from vector register VRB into two signed 64-bit doublewords in VRT, sign-extending each word. This instruction is part of the VMX (AltiVec) category and does not update condition registers.

Pseudocode Operation

VRT[0:63] ← EXTS(VRB[0:31])
VRT[64:127] ← EXTS(VRB[32:63])

Programming Note

This instruction is used to extract the high signed word from each vector element of VRB and store it in the corresponding doubleword element of VRT. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector Unavailable exception will be raised. The operation is performed on 32-bit elements, so alignment requirements are based on these boundaries.

Example

vupkhsw v1, v3

Encoding

Binary Layout
0
0
VRT
6
VRB
11
0
31
0
0
0
0
0
0
0
0
0
0
0
0
 
Format VX-form
Opcode 0x1000064E
Extension VMX (AltiVec)

Operands

  • VRT
    Target Vector Register
  • VRB
    Source Vector Register