xvnegdp

VSX Vector Negate Double-Precision

xvnegdp XT, XB

Negates the contents of a double-precision floating-point vector register and stores the result in another vector register.

Details

The instruction negates each doubleword element of the source vector register VSR[XB] and stores the results in the target vector register VSR[XT].

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()
do i = 0 to 3
    src ←VSR[32×BX+B].dword[i]
    VSR[32×TX+T].dword[i] ←bfp64_NEGATE(src)
end

Programming Note

This instruction is used to negate each double-precision floating-point element in a vector. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the appropriate bit in the MSR register. The operation processes four elements per vector register, so ensure proper alignment of data for optimal performance. This instruction operates at the user privilege level and will raise an exception if VSX is not available.

Example

xvnegdp vs1, vs3

Encoding

Binary Layout
60
6
XT
11
0
16
XB
21
489
 
Format XX2-form
Opcode 0xF00001E9
Extension VSX
Registers Altered MSR

Operands

  • XT
    Target
  • XB
    Source