xvcvuxddp

VSX Vector Convert with round Unsigned Doubleword to Double-Precision format

xvcvuxddp VRT, VRA, VRB

Converts an unsigned doubleword vector element to a double-precision floating-point value.

Encoding

Binary Layout

111100

0:5

VRT

6:10

//

11:15

VRA

16:20

11110

21:30

1000

31

 

Format XX2-form

Opcode 0xF00007A0

Extension VSX

Operands

• VRT
  Target Vector Register
• VRA
  Source Vector Register
• VRB
  Source Vector Register

Example

xvcvuxddp v1, v2, v3

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For each doubleword element in the source vector register VRB, the instruction converts the unsigned 64-bit integer value to a double-precision floating-point value and places the result in the corresponding doubleword element of the target vector register VRT. The conversion uses the current rounding mode. Two elements are processed in parallel, one per doubleword lane.

Operation

do i = 0 to 1
  VRT.dword[i] ← ConvertUnsignedFixed64ToFP64(VRB.dword[i])

Programming Note

This instruction is useful for converting unsigned 64-bit integers in a vector to double-precision floating-point numbers. Ensure that the source vector elements are correctly aligned and consider the current rounding mode's effect on conversion results. This operation processes two elements per cycle, making it efficient for bulk conversions.