xvcvdpsxws

Vector Convert Double-Precision to Signed Word format with round to zero

xvcvdpsxws XT,XB

Converts double-precision floating-point values in a vector to signed 32-bit integers with rounding towards zero.

Encoding

Binary Layout

60

0:5

XT

6:10

/

11:15

XB

16:20

864

21:31

 

Format X-form

Opcode 0xF0000360

Extension VSX

Operands

• XT
  Target Vector Register
• XB
  Source Vector Register

Example

xvcvdpsxws vs1, vs3

Registers Altered

FPSCR (FX, XX, VXSNAN, VXCVI)

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Converts each double-precision floating-point element in XB to a signed 32-bit integer in XT, rounding towards zero (truncation). This is a VSX instruction that operates on vector elements independently. No condition registers or status fields are affected by this instruction.

Operation

for i in 0 to 1 do
  XT[i*64:(i+1)*64-1] ← CVTDP_TO_SI_RZ(XB[i*64:(i+1)*64-1])
end for

Programming Note

xvcvdpsxws rounds using Round towards Zero rounding mode. Previous versions of the architecture allowed the contents of words 1 and 3 of the result register to be undefined. However, all processors that support this instruction write the result into words 0 and 1 and words 2 and 3 of the result register.