xvcvdpsxws

Vector Convert Double-Precision to Signed Word format with round to zero

xvcvdpsxws XT,XB

Converts double-precision floating-point values in a vector to signed 32-bit integers with rounding towards zero.

Details

The xvcvdpsxws instruction converts the double-precision floating-point value in doubleword element i of VSR[XB] (where i∈{0,1}) to a 32-bit signed integer format. The result is stored in word elements 2×i and 2×i+1 of VSR[XT]. If the source value is outside the range of a 32-bit signed integer, it is saturated to the nearest representable value.

Pseudocode Operation

for i = 0 to 1 do
    src <- VSR[XB][i]
    if src is a QNaN then
        T(Nmin), fx(VXCVI), fx(VXSNAN)
    else if src is a SNaN then
        T(Nmin), fx(VXCVI), fx(VXSNAN)
    else if src ≤ Nmin-1 then
        T(Nmin), fx(VXCVI)
    else if Nmin-1 < src < Nmin then
        if FPSCR.XE = 0 then
            T(Nmin), fx(XX)
        else
            fx(XX), error()
    else if src = Nmin then
        if FPSCR.VE = 0 then
            T(Nmin)
        else
            T(f2i(trunc(src))), fx(XX)
    else if Nmin < src < Nmax then
        if FPSCR.XE = 0 then
            T(f2i(trunc(src))), fx(XX)
        else
            fx(XX), error()
    else if src = Nmax then
        if FPSCR.VE = 0 then
            T(Nmax)
        else
            T(Nmax), fx(XX)
    else if Nmax < src < Nmax+1 then
        if FPSCR.XE = 0 then
            T(Nmax), fx(XX)
        else
            fx(XX), error()
    else if src ≥ Nmax+1 then
        T(Nmax), fx(VXCVI)
    end if
end for

Programming Note

['xvcvdpsxws rounds using Round towards Zero rounding mode.', 'Previous versions of the architecture allowed the contents of words 1 and 3 of the result register to be undefined. However, all processors that support this instruction write the result into words 0 and 1 and words 2 and 3 of the result register.']

Example

xvcvdpsxws vs1, vs3

Encoding

Binary Layout

864

Format X-form

Opcode 0xF0000360

Extension VSX

Registers Altered FPSCR (FX, XX, VXSNAN, VXCVI)

Operands

XT
Target Vector Register
XB
Source Vector Register