xvmaddasp

Vector Multiply-Add Single-Precision Type-A

xvmaddasp XT,XA,XB

Performs a single-precision floating-point multiply-add operation on vector elements.

Details

The xvmaddasp instruction multiplies the single-precision floating-point value in VSR[XA] by the single-precision floating-point value in VSR[XT], adds the result to the single-precision floating-point value in VSR[XB], and stores the result back into VSR[XT].

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0
do i = 0 to 3
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP32(VSR[32×AX+A].word[i])
    src2 ←bfp_CONVERT_FROM_BFP32(VSR[32×TX+T].word[i])
    src3 ←bfp_CONVERT_FROM_BFP32(VSR[32×BX+B].word[i])
    v   ←bfp_MULTIPLY_ADD(src1,src3,src2)
    rnd ←bfp_ROUND_TO_BFP32(FPSCR.RN,v)
    vresult.word[i] ←bfp32_CONVERT_FROM_BFP(rnd)

    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vximz_flag=1 then SetFX(FPSCR.VXIMZ)
    if vxisi_flag=1 then SetFX(FPSCR.VXISI)
    if ox_flag=1 then SetFX(FPSCR.OX)
    if ux_flag=1 then SetFX(FPSCR.UX)
    if xx_flag=1 then SetFX(FPSCR.XX)

    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vximz_flag) | (FPSCR.VE & vxisi_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.XE & xx_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←result

Programming Note

The xvmaddasp instruction is commonly used for performing vectorized single-precision floating-point multiply-add operations. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid a VSX_Unavailable exception. Be cautious of potential exceptions such as VXSNAN, VXIMZ, Vxisi, OX, UX, and XX, which can be set based on the operation's result and FPSCR settings. The instruction operates on 128-bit vectors, so ensure proper alignment for optimal performance.

Example

xvmaddasp vs1, vs2, vs3

Encoding

Binary Layout
6
0
T
16
A
11
B
6
AX
29
BX
24
TX
21
 
Format XX3-form
Opcode 0xF0000208
Extension VSX
Registers Altered FPSCR, VXSNAN, VXIMZ, Vxisi, OX, UX, XX

Operands

  • XT
    Destination Vector Register
  • XA
    Source Vector Register
  • XB
    Source Vector Register