xvmaddasp

Vector Multiply-Add Single-Precision Type-A

xvmaddasp XT,XA,XB

Performs a single-precision floating-point multiply-add operation on vector elements.

Details

Performs a vector multiply-add operation on single-precision floating-point elements, computing XT = XT + (XA × XB) for each element. The operation is fused, rounding only once at the end. This instruction requires VSX support and updates FPSCR exception flags based on the operation results.

Pseudocode Operation

for i ∈ {0, 1, 2, 3}
  XT[i*32:(i+1)*32] ← XT[i*32:(i+1)*32] + (XA[i*32:(i+1)*32] × XB[i*32:(i+1)*32])
FPSCR ← update_exception_flags(FPSCR, results)

Programming Note

The xvmaddasp instruction is commonly used for performing vectorized single-precision floating-point multiply-add operations. Ensure that the VSX (Vector Scalar Extensions) are enabled in the MSR register to avoid a VSX_Unavailable exception. Be cautious of potential exceptions such as VXSNAN, VXIMZ, Vxisi, OX, UX, and XX, which can be set based on the operation's result and FPSCR settings. The instruction operates on 128-bit vectors, so ensure proper alignment for optimal performance.

Example

xvmaddasp vs1, vs2, vs3

Encoding

Binary Layout
6
0
T
16
A
11
B
6
AX
29
BX
24
TX
21
 
Format XX3-form
Opcode 0xF0000208
Extension VSX
Registers Altered FPSCR, VXSNAN, VXIMZ, Vxisi, OX, UX, XX

Operands

  • XT
    Destination Vector Register
  • XA
    Source Vector Register
  • XB
    Source Vector Register