xxmrghd

VSX Vector Merge High Doubleword

xxmrghd XT, XA, XB

Merges high doublewords from XA and XB.

Encoding

Binary Layout

60

0:5

XT

6:10

XA

11:15

XB

16:20

144

21:31

 

Format XX3-form

Opcode 0xF0000050

Extension VSX

Operands

• XT
  Target
• XA
  Src A
• XB
  Src B

Example

xxmrghd vs1, vs2, vs3

Registers Altered

MSR

Related

More in VSX

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Merges the two high-order doubleword elements from VSR[XA] and VSR[XB] into VSR[XT]. Element 0 of XA is placed in element 0 of XT, and element 0 of XB is placed in element 1 of XT. This is a vector permutation instruction with no floating-point status updates.

Operation

VSR[XT].element[0] ← VSR[XA].element[0]
VSR[XT].element[1] ← VSR[XB].element[0]

Programming Note

The xxmrghd instruction is used to merge the high doublewords from two source vector registers into a target vector register. Ensure that the VSX facility is enabled by checking and setting the appropriate bit in the MSR register. Be cautious with the DM bits, as they determine which source doubleword is merged into the target register. This instruction operates at the user privilege level and will raise an exception if the VSX facility is not available.