xvtstdcsp

VSX Vector Test Data Class Single-Precision

xvtstdcsp XT,XB,DCMX

Tests each single-precision floating-point element in a vector against specified data classes and sets the corresponding elements in another vector based on the match.

Details

This instruction tests each single-precision floating-point element in VSR[XB] against the data classes specified by DCMX. If an element matches one of the specified data classes, the corresponding element in VSR[XT] is set to 0xFFFF_FFFF; otherwise, it is set to 0x0000_0000.

Pseudocode Operation

if MSR.VSX=0 then VSX_Unavailable()

DCMX ←dc || dm || dx
do i = 0 to 3
    src           ←VSR[32×BX+B].word[i]
    sign         ←src.bit[0]
    exponent      ←src.bit[1:8]
    fraction      ←src.bit[9:31]
    class.Infinity ←(exponent = 0xFF) & (fraction  = 0)
    class.NaN     ←(exponent = 0xFF) & (fraction != 0)
    class.Zero    ←(exponent = 0x00) & (fraction  = 0)
    class.Denormal ←(exponent = 0x00) & (fraction != 0)

    match ←
        (DCMX.bit[0] & class.NaN)              |
        (DCMX.bit[1] & class.Infinity & !sign) |
        (DCMX.bit[2] & class.Infinity &  sign) |
        (DCMX.bit[3] & class.Zero     & !sign) |
        (DCMX.bit[4] & class.Zero     &  sign) |
        (DCMX.bit[5] & class.Denormal & !sign) |
        (DCMX.bit[6] & class.Denormal &  sign)

    if match = 1 then
        VSR[32×TX+T].dword[i] ←0xFFFF_FFFF
    else
        VSR[32×TX+T].dword[i] ←0x0000_0000
end

Programming Note

This instruction is useful for identifying specific data classes in single-precision floating-point vectors. Ensure that the VSX (Vector Scalar Extensions) are enabled by checking and setting the appropriate bits in the MSR register. The instruction does not require any special alignment, but it operates on 32-bit elements within the vector registers. Be cautious with the DCMX mask to avoid unintended matches, as incorrect settings can lead to all elements being set to zero or all being set to 0xFFFFFFFF.

Example

xvtstdcsp vs1, vs3, 0

Encoding

Binary Layout
110000
0
T
6
dx
8
B
10
13
16
dc
17
5
19
dm
21
BX
22
TX
26
 
Format XX2-form
Opcode 0xF00006A8
Extension VSX
Registers Altered None

Operands

  • XT
    Target Vector Register
  • XB
    Source Vector Register
  • DCMX
    Data Class Mask (concatenation of dc, dm, and dx)