vavgsb

Vector Average Signed Byte

vavgsb vD, vA, vB

Performs a signed byte-wise average of two vector registers and stores the result in another vector register.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1282

21:31

Format VA-form

Opcode 0x10000502

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Src B
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register

Example

vavgsb vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vavgsb, each byte element of VSR[VRA+32] is added to the corresponding byte element of VSR[VRB+32], incremented by 1, then right-shifted by 1 bit. The low-order 8 bits of the result are placed into the corresponding byte element of VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    src1 ←EXTS(VSR[VRA+32].byte[i])
    src2 ←EXTS(VSR[VRB+32].byte[i])
    VSR[VRT+32].byte[i] ←CHOP8((src1 + src2 + 1) >> 1)
end

Programming Note

The vavgsb instruction performs a signed byte average, rounding up by adding 1 before shifting. Ensure that the Vector Facility is enabled in the MSR register to avoid exceptions. This operation is useful for blending two images or averaging data with precision.