xvdivdp

VSX Vector Divide Double-Precision

xvdivdp XT, XA, XB

Divides the contents of two vector registers and places the result in another vector register.

Details

For xvdivdp, each double-precision floating-point operand in doubleword elements of VSR[XA] is divided by the corresponding operand in VSR[XB], producing a quotient that is normalized and rounded to double precision. The result is placed into doubleword elements of VSR[XT].

Pseudocode Operation

for i = 0 to 1 do
    src1 <- VSR[XA][i]
    src2 <- VSR[XB][i]
    if src2 is NaN then
        v <- Q(src2)
        vxsnan_flag <- 1
    else if src1 is NaN then
        v <- Q(src1)
        vxsnan_flag <- 1
    else if src1 is +Infinity and src2 is +Infinity then
        v <- +Infinity
        vxidi_flag <- 1
    else if src1 is -Infinity and src2 is -Infinity then
        v <- +Infinity
        vxidi_flag <- 1
    else if src1 is +Infinity and src2 is -Infinity then
        v <- -Infinity
        vxidi_flag <- 1
    else if src1 is -Infinity and src2 is +Infinity then
        v <- -Infinity
        vxidi_flag <- 1
    else if src1 is +Zero and src2 is +Zero then
        v <- +Zero
        zx_flag <- 1
    else if src1 is -Zero and src2 is -Zero then
        v <- +Zero
        zx_flag <- 1
    else if src1 is +Zero and src2 is -Zero then
        v <- -Zero
        zx_flag <- 1
    else if src1 is -Zero and src2 is +Zero then
        v <- -Zero
        zx_flag <- 1
    else if src1 is +Infinity or src1 is -Infinity and src2 is not zero then
        v <- Q(src2)
        vxidi_flag <- 1
    else if src2 is +Zero or src2 is -Zero and src1 is not zero then
        v <- dQNaN
        vxzdz_flag <- 1
    else
        v <- D(src1, src2)
    VSR[VRT][i] <- v

Programming Note

The xvdivdp instruction performs element-wise division of double-precision floating-point numbers. Ensure that the input vectors are properly aligned and that the destination vector is distinct to avoid unintended data corruption. Be aware of special cases like division by zero, which sets VXZDZ flag and results in a NaN. Handle exceptions by checking the FPSCR register flags after execution.

Example

xvdivdp vs1, vs2, vs3

Encoding

Binary Layout
60
0
XT
6
XA
11
XB
16
120
21
 
Format XX3-form
Opcode 0xF0000078
Extension VSX
Registers Altered FPSCR, VXSNAN, VXIDI, VXZDZ, OX, UX, ZX, XX

Operands

  • XT
    Target
  • XA
    Src A
  • XB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register (Dividend)
  • VRB
    Source Vector Register (Divisor)