xsrsqrtesp

VSX Scalar Reciprocal Square Root Estimate (Single-Precision)

xsrsqrtesp XT,XB

Estimates the reciprocal square root of a single-precision floating-point value.

Encoding

Binary Layout

30 31

Format XX2-form

Opcode 0xF0000028

Extension VSX

Operands

XT
Target Vector-Scalar Register
XB
Source Vector-Scalar Register
FRT
Target Floating Point Register
FRB
Source Floating Point Register

Example

xsrsqrtesp vs1, vs3

Registers Altered

FPSCR (FPRF, FX, OX, UX, ZX, VXSNAN, VXSQRT, FR, FI, XX)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The instruction estimates the reciprocal square root of a single-precision floating-point value in doubleword element 0 of VSR[XB] and places the result into doubleword element 0 of VSR[XT]. Doubleword element 1 of VSR[XT] is set to 0.

Operation

if MSR.VSX=0 then VSX_Unavailable()
reset_xflags()
src ← bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[0])
v ← bfp_RECIPROCAL_SQUARE_ROOT_ESTIMATE(src)
rnd ← bfp_ROUND_TO_BFP32(FPSCR.RN, v)
result32 ← bfp32_CONVERT_FROM_BFP(rnd)
result64 ← bfp64_CONVERT_FROM_BFP(rnd)
if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
if vxsqrt_flag=1 then SetFX(FPSCR.VXSQRT)
if ox_flag=1 then SetFX(FPSCR.OX)
if ux_flag=1 then SetFX(FPSCR.UX)
if 0bU then SetFX(FPSCR.XX)
if zx_flag=1 then SetFX(FPSCR.ZX)
vx_flag ← vxsnan_flag | vxsqrt_flag
vex_flag ← FPSCR.VE & vx_flag
zex_flag ← FPSCR.ZE & zx_flag
if vex_flag=0 & zex_flag=0 then do
    VSR[32×TX+T].dword[1] ← 0x0000_0000_0000_0000
    FPSCR.FPRF ← fprf_CLASS_BFP32(result32)
    FPSCR.FR ← 0bU
    FPSCR.FI ← 0bU
else do
    FPSCR.FR ← 0b0
    FPSCR.FI ← 0b0
end

Programming Note

Previous versions of the architecture allowed the contents of doubleword 1 of the result register to be undefined. However, all processors that support this instruction write 0s into doubleword 1 of the result register, as is required by this version of the architecture.