vsrab

Vector Shift Right Algebraic Byte

vsrab vD, vA, vB

Shifts each byte of the source vector right by a specified number of bits, filling vacated bits with copies of the sign bit.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

772

21:31

Format VX-form

Opcode 0x10000304

Extension VMX (AltiVec)

Operands

vD
Target
vA
Data
vB
Shift
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Shift Amount Vector Register

Example

vsrab vd, va, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vsrab, each byte element in VSR[VRA+32] is shifted right by the number of bits specified in the low-order 3 bits of the corresponding byte element in VSR[VRB+32]. The result is placed into the corresponding byte element in VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 15
    src1 ← VSR[VRA+32].byte[i]
    src2 ← VSR[VRB+32].byte[i].bit[5:7]
    VSR[VRT+32].byte[i] ← CHOP8(EXTS(src1) >> src2)
end

Programming Note

The vsrab instruction performs a right algebraic shift on each byte of the source vector, using the low-order 3 bits of the corresponding byte in the second source vector as the shift amount. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates at the user privilege level and does not generate exceptions for valid shifts; however, invalid shifts (e.g., shifting more than 7 bits) will result in undefined behavior.