vrlwnm

Vector Rotate Left Word then AND with Mask

vrlwnm VRT,VRA,VRB

Rotates each word element of the source vector left by a specified number of bits and then performs a bitwise AND operation with a mask.

Details

For vrlwnm, each word element of VSR[VRA+32] is rotated left by the number of bits specified in the corresponding word element of VSR[VRB+32]. The result is then ANDed with a mask generated from bits 11:15 and 19:23 of the same source vector element. The final result is stored in VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 3
    src1.word[0] ← VSR[VRA+32].word[i]
    src1.word[1] ← VSR[VRA+32].word[i]
    src2 ← VSR[VRB+32].word[i]
    b ← src2.bit[11:15]
    e ← src2.bit[19:23]
    n ← src2.bit[27:31]
    r ← src1.bit[n:n+31]
    m ← MASK(b, e)
    VSR[VRT+32].word[i] ← r & m

Programming Note

The vrlwnm instruction is useful for performing bitwise operations on vector elements. Ensure that the mask bits (11:15 and 19:23) are set correctly to achieve the desired AND operation. This instruction operates at the user privilege level and does not generate exceptions under normal conditions, but it requires the vector facility to be enabled in the MSR register.

Example

vrlwnm v1, v2, v3

Encoding

Binary Layout
4
0
VRT
6
VRA
11
VRB
16
 
Format VX-form
Opcode 0x10000185
Extension VMX (AltiVec)
Registers Altered None

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register