vexpandbm

Vector Expand Byte Mask

vexpandbm vD, vB

Expands the mask from bit 0 of each byte element in the source VSR to all bits in the corresponding element in the target VSR.

Encoding

Binary Layout

4

0:5

VRT

6:10

0

11:15

VRB

16:20

1602

21:31

 

Format VX-form

Opcode 0x10000642

Extension VMX (AltiVec)

Operands

• vD
  Target
• vB
  Source
• VRT
  Target Vector Register
• VRB
  Source Vector Register

Example

vexpandbm vd, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Expands the mask bit (bit 0) of each byte element in vB to all 8 bits of the corresponding byte in vD. If vB[byte][0] = 1, the entire byte in vD becomes 0xFF; if vB[byte][0] = 0, the entire byte in vD becomes 0x00. This is a VMX extension instruction with no condition register or status flag updates.

Operation

for i in 0 to 15 do
  if vB[i*8] = 1 then
    vD[i*8:(i+1)*8] ← 0xFF
  else
    vD[i*8:(i+1)*8] ← 0x00

Programming Note

The vexpandbm instruction is useful for creating masks where each byte is either all zeros or all ones based on the least significant bit of the corresponding source byte. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This operation is efficient for processing data in parallel across multiple bytes.