vextduwvlx

Vector Extract Double Unsigned Word to VSR using GPR-specified Left-Index VA-form

vextduwvlx VRT,VRA,VRB,RC

Extracts a doubleword from the concatenation of two vector registers based on an index specified in a general-purpose register.

Details

The instruction extracts a doubleword from the concatenation of the contents of VSR[VRA+32] and VSR[VRB+32] based on the index derived from bits 59:63 of GPR[RC]. The extracted bytes are zero-extended into the first doubleword of VSR[VRT+32], and the second doubleword is set to zero.

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
index ← GPR[RC].bit[59:63]
src.qword[0] ← VSR[VRA+32]
src.qword[1] ← VSR[VRB+32]
VSR[VRT+32].dword[0] ← EXTZ64(src.byte[index:index+3])
VSR[VRT+32].dword[1] ← 0x0000_0000_0000_0000
if index > 28 then
    undefined result

Programming Note

This instruction is used to extract a doubleword from the concatenation of two vector registers based on an index specified in a general-purpose register. Ensure that the index does not exceed 28 to avoid undefined results. The operation requires the VEC bit in the Machine State Register (MSR) to be set; otherwise, a Vector Unavailable exception will occur.

Example

vextduwvlx v1, v2, v3, r6

Encoding

Binary Layout
000100
0
VRT
6
VRA
11
VRB
16
RC
21
011100
26
 
Format VA-form
Opcode 0x1000001C
Extension VMX (AltiVec)

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register
  • RC
    General Purpose Register containing the index