vextsh2d

Vector Extend Sign Halfword To Doubleword

vextsh2d vD, vB

Extends the sign of each halfword in a vector to doubleword.

Details

The vextsh2d instruction sign-extends the signed integer in bits 48:63 of each doubleword element from the source vector register (VRB) and places the result into the corresponding doubleword element of the destination vector register (VRT). This operation is performed for each integer value i from 0 to 1.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 1
   src ←VSR[VRB+32].dword[i].bit[48:63]
   VSR[VRT+32].dword[i] ←EXTS64(src)
end

Programming Note

This instruction is used for sign-extending the upper 16 bits of each doubleword in a vector from VRB to VRT. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation processes two elements per instruction execution.

Example

vextsh2d vd, vb

Encoding

Binary Layout

1862

Format VX-form

Opcode 0x10000746

Extension VMX (AltiVec)

Registers Altered MSR

Operands

vD
Target
vB
Source
VRT
Target Vector Register
VSRC
Source Vector Register