vextsh2d

Vector Extend Sign Halfword To Doubleword

vextsh2d vD, vB

Extends the sign of each halfword in a vector to doubleword.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1862

21:31

Format VX-form

Opcode 0x10190602

Extension VMX (AltiVec)

Operands

vD
Target
vB
Source
VRT
Target Vector Register
VSRC
Source Vector Register

Example

vextsh2d vd, vb

Registers Altered

MSR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Sign-extends each of two 16-bit halfwords in the source vector to 64-bit doublewords, filling the upper bits with the sign bit, and stores the result in the destination vector. The instruction operates on the two halfwords in the lower 32 bits of the source. No condition flags are affected; this is a VMX/AltiVec instruction.

Operation

vD[0:63] ← (vB[0] replicated to 48 bits) || vB[0:15]
vD[64:127] ← (vB[16] replicated to 48 bits) || vB[16:31]

Programming Note

This instruction is used for sign-extending the upper 16 bits of each doubleword in a vector from VRB to VRT. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise an exception. The operation processes two elements per instruction execution.