xvcvspuxws

Vector Convert with round to zero Single-Precision to Unsigned Word format

xvcvspuxws XT,XB

Converts a single-precision floating-point value to an unsigned word using round towards zero.

Details

The instruction converts each element of the source vector (VSR[XB]) from single-precision floating-point format to an unsigned 32-bit integer, rounding towards zero. If the result is out of range, it saturates to either 0x0000_0000 or 0xFFFF_FFFF.

Pseudocode Operation

for i = 0 to 3 do
    src <- VSR[XB][i]
    if src ≤ Nmin-1 then
        T(Nmin)
    else if Nmin-1 < src < Nmin then
        if FPSCR.VE = 0 then
            T(Nmin)
        else
            fx(VXCVI), error()
        end if
    else if src = Nmin then
        T(Nmin)
    else if Nmin < src < Nmax then
        if FPSCR.XE = 0 then
            T(f2i(trunc(src)))
        else
            fx(XX), error()
        end if
    else if src = Nmax then
        T(Nmax)
    else if Nmax < src < Nmax+1 then
        if FPSCR.XE = 0 then
            T(Nmax)
        else
            fx(XX), error()
        end if
    else if src ≥ Nmax+1 then
        if FPSCR.VE = 0 then
            T(Nmin)
        else
            fx(VXCVI), error()
        end if
    else if src is a QNaN then
        if FPSCR.VE = 0 then
            T(Nmin)
        else
            fx(VXCVI), error()
        end if
    else if src is a SNaN then
        if FPSCR.VE = 0 then
            T(Nmin)
        else
            fx(VXCVI), fx(VXSNAN), error()
        end if
    end if
end for

Programming Note

xvcvspuxws rounds using Round towards Zero rounding mode. For other rounding modes, software must use a Round to Single-Precision Integer instruction that corresponds to the desired rounding mode.

Example

xvcvspuxws vs1, vs3

Encoding

Binary Layout
60
0
XT
6
/
11
XB
16
544
21
 
Format XX2-form
Opcode 0xF0000220
Extension VSX
Registers Altered FPSCR, VXSNAN, VXCVI, XX

Operands

  • XT
    Target Vector Register
  • XB
    Source Vector Register