mtfsf

Move To FPSCR Fields

mtfsf FLM,FRB,L,W

Moves the contents of a floating-point register into specified fields of the FPSCR.

Encoding

Binary Layout

FLM

FRB

711

Format XFL-form

Opcode 0xFC00058E

Extension Floating-Point

Operands

FLM
Field Mask
FRB
Source
L
Load Control Bit
W
Word Select Bit

Example

mtfsf 0xFF, f3, 0, 0

Registers Altered

FPSCR, CR1

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The FPSCR is modified as specified by the FLM, L, and W fields. If L=0, the contents of register FRB are placed into the FPSCR under control of the W field and the field mask specified by FLM. If L=1, the contents of register FRB are placed into the FPSCR.

Operation

if 'mtfsf' then
    if L=0 then
        for i from 0 to 7 do
            if FLMi=1 then
                FPSCR[k] <- FRB[i+8*(1-W)]
            end if
        end for
    else if L=1 then
        FPSCR <- FRB
    end if
end if

Extended Mnemonics

Extended Mnemonic	Equivalent Instruction

Programming Note

Bits 33 and 34 (FEX and VX) cannot be explicitly reset. If L=1 or if L=0 and FPSCR32:35 is specified, bits 32 (FX) and 35 (OX) are set to the values of (FRB)32 and (FRB)35.