mffsl

Move From FPSCR Lightweight

mffsl FRT

Moves the control and non-sticky status bits from the FPSCR to a general-purpose register.

Encoding

Binary Layout

63

0:5

FRT

6:10

///

11:30

0

31

 

Format X-form

Opcode 0xFC00048E

Extension Floating-Point

Operands

• FRT
  Target General Purpose Register

Example

mffsl f1

Registers Altered

FPSCR

Related

More in Floating-Point

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of the control bits in the FPSCR (bits 29:31) and the non-sticky status bits (bits 45:51) are placed into the corresponding bits in register FRT. All other bits in register FRT are set to 0.

Operation

FRT <- (FPSCR[29:31] || FPSCR[45:51])

Programming Note

mffsl permits software to read the control and non-sticky status bits in the FPSCR without the higher latency typically associated with accessing the sticky status bits.