psq_l

Paired Single Quantized Load

psq_l FRT, D(RA), W, I

Loads a paired single from memory (Embedded/Legacy).

Encoding

Binary Layout

56

0:5

FRT

6:10

RA

11:15

W

16:20

I

21:30

6

31

 

Format X-form

Opcode 0xE0000006

Extension VMX (AltiVec)

Operands

• FRT
  Target
• D
  Disp
• RA
  Base
• W
  Width
• I
  Scale

Example

psq_l f1, 0(r4), 0, 0

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Loads a pair of single-precision floating-point values from memory into an FPR, with optional quantization/scaling applied. The W field controls element width, and the I field specifies the scale factor applied during load. This is a legacy VMX/AltiVec instruction primarily found on embedded PowerPC implementations.

Operation

EA ← (RA = 0 ? 0 : GPR[RA]) + D
data ← [EA] (quantized width W, scale I)
FPR[FRT] ← float32_pair(data)