ps_madd

Paired Single Multiply-Add

ps_madd FRT, FRA, FRC, FRB

Multiply-Add on paired singles.

Encoding

Binary Layout

60

0:5

FRT

6:10

FRA

11:15

FRB

16:20

FRC

21:25

29

26:31

 

Format A-form

Opcode 0xF000001D

Extension VMX (AltiVec)

Operands

• FRT
  Target
• FRA
  Src A
• FRC
  Src C
• FRB
  Src B

Example

ps_madd f1, f2, f4, f3

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Performs multiply-add on two pairs of single-precision floating-point values element-wise, computing FRA × FRC + FRB and storing the result in FRT. All three source registers contribute to the operation, with each element pair computed independently. May set FPSCR status flags if exceptions occur.

Operation

FPR[FRT].upper ← FPR[FRA].upper × FPR[FRC].upper + FPR[FRB].upper
FPR[FRT].lower ← FPR[FRA].lower × FPR[FRC].lower + FPR[FRB].lower