vavgsh

Vector Average Signed Halfword

vavgsh vD, vA, vB

Performs a signed halfword average operation on vector elements.

Details

For vavgsh, the sum of the contents of each corresponding pair of halfwords from VSR[VRA+32] and VSR[VRB+32] is calculated, incremented by 1, shifted right by 1 bit, and then placed into the corresponding halfword in VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 7
    src1 ←EXTS(VSR[VRA+32].hword[i])
    src2 ←EXTS(VSR[VRB+32].hword[i])
    VSR[VRT+32].hword[i] ← CHOP16((src1 + src2 + 1) >> 1)
end

Programming Note

The vavgsh instruction performs a signed halfword average, rounding up by adding 1 before shifting. Ensure that the vector facility is enabled in the MSR register to avoid exceptions. This operation processes each pair of halfwords independently, so alignment requirements are minimal.

Example

vavgsh vd, va, vb

Encoding

Binary Layout
0
0
VRT
6
VRA
11
VRB
16
1346
21
 
Format VA-form
Opcode 0x10000542
Extension VMX (AltiVec)
Registers Altered MSR

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register