sthcix
Store Halfword Caching Inhibited Indexed X-form
Stores a halfword from a general-purpose register to memory, with caching inhibited.
Details
The contents of the lower 16 bits (bits 48:63) of register RS are stored into the halfword in memory addressed by the effective address (EA). The EA is the sum of the contents of register RA and register RB. The store is performed with caching inhibited, meaning the data is written directly to memory bypassing the cache. This instruction is a privileged hypervisor instruction available in Book III.
Pseudocode Operation
EA ← (RA) + (RB)
MEM(EA, 2) ← (RS)[48:63]Programming Note
This instruction is used for storing data directly to memory without caching, which can be useful for ensuring data consistency in hypervisor environments. It requires supervisor privilege level and should be used with caution as it bypasses the cache, potentially affecting performance. Ensure that registers RA and RB contain valid addresses, and RS contains the data to be stored in its lower 16 bits.
Example
Encoding
Operands
-
RT
Target General Purpose Register -
RB
Base Address General Purpose Register -
RA
Index General Purpose Register