vctzw

Vector Count Trailing Zeros Word

vctzw vD, vB

Counts the number of trailing zero bits in each word element of a vector register.

Encoding

Binary Layout

4

0:5

vD

6:10

0

11:15

vB

16:20

1922

21:31

 

Format VX-form

Opcode 0x101E0602

Extension VMX (AltiVec)

Operands

• vD
  Target
• vB
  Source
• VRT
  Target Vector Register
• VRB
  Source Vector Register

Example

vctzw vd, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vctzw, the number of consecutive zero bits starting at bit 31 of each word element in VSR[VRB+32] is counted and placed into the corresponding word element in VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    n ←0
do while n < 32
    if VSR[VRB+32].word[i].bit[31-n] = 0b1 then
        leave
    n ←n + 1
end
VSR[VRT+32].word[i] ←CHOP32(EXTZ(n))
end

Programming Note

The vctzw instruction counts the number of trailing zeros in each word element of a vector register. Ensure that the Vector Facility is enabled by checking and setting the VEC bit in the MSR register. This instruction operates on 32-bit words, so input data must be aligned accordingly. The result is stored in another vector register, preserving the original data unless explicitly overwritten.