vextddvlx

Vector Extract Double Doubleword to VSR using GPR-specified Left-Index VA-form

vextddvlx VRT,VRA,VRB,RC

Extracts a doubleword from the concatenation of two vector registers based on an index specified in a general-purpose register.

Details

The instruction extracts a doubleword from the concatenation of the contents of VSR[VRA+32] and VSR[VRB+32] using an index derived from bits 59:63 of GPR[RC]. The extracted byte elements are placed into doubleword 0 of VSR[VRT+32], while doubleword 1 is set to zero.

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
index ← GPR[RC].bit[59:63]
src.qword[0] ← VSR[VRA+32]
src.qword[1] ← VSR[VRB+32]
VSR[VRT+32].dword[0] ← src.byte[index:index+7]
VSR[VRT+32].dword[1] ← 0x0000_0000_0000_0000

Programming Note

This instruction is useful for extracting a specific doubleword from two VSX registers based on an index specified in a GPR. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, it will raise a Vector Unavailable exception. The index is derived from bits 59:63 of the GPR, so ensure these bits are correctly set to access the desired doubleword. Note that the upper doubleword of the destination register is always zeroed.

Example

vextddvlx v1, v2, v3, r6

Encoding

Binary Layout
0
4
VRT
6
VRA
11
VRB
16
RC
21
 
Format VA-form
Opcode 0x7C000000
Extension VMX (AltiVec)

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register
  • RC
    General Purpose Register containing the index