xvadddp

VSX Vector Add Double-Precision

xvadddp XT, XA, XB

Adds the contents of two double-precision floating-point elements from two vector registers and places the result into a target vector register.

Encoding

Binary Layout

0:10

11:15

16:20

21:25

26:30

Format XX3-form

Opcode 0xF0000300

Extension VSX

Operands

XT
Target
XA
Source A
XB
Source B

Example

xvadddp 0, 1, 2

// 2-way parallel double add.

Registers Altered

FPSCR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For xvadddp, the sum of the contents of doubleword element i of VSR[XA] and VSR[XB] is placed into doubleword element i of VSR[XT].

Operation

if MSR.VSX=0 then VSX_Unavailable()

ex_flag ←0b0
do i = 0 to 1
    reset_xflags()
    src1 ←bfp_CONVERT_FROM_BFP64(VSR[32×AX+A].dword[i])
    src2 ←bfp_CONVERT_FROM_BFP64(VSR[32×BX+B].dword[i])
    v    ←bfp_ADD(src1,src2)
    rnd  ←bfp_ROUND_TO_BFP64(0b0,FPSCR.RN,v)
    vresult.dword[i] ←bfp64_CONVERT_FROM_BFP(rnd)

    if vxsnan_flag=1 then SetFX(FPSCR.VXSNAN)
    if vxisi_flag=1 then SetFX(FPSCR.VXISI)
    if ox_flag=1 then SetFX(FPSCR.OX)
    if ux_flag=1 then SetFX(FPSCR.UX)
    if xx_flag=1 then SetFX(FPSCR.XX)

    ex_flag ←ex_flag | (FPSCR.VE & vxsnan_flag) | (FPSCR.VE & vxisi_flag) | (FPSCR.OE & ox_flag) | (FPSCR.UE & ux_flag) | (FPSCR.XE & xx_flag)
end

if ex_flag=0 then VSR[32×TX+T] ←vresult

Programming Note

This instruction is commonly used for adding two double-precision floating-point numbers stored in VSX registers. Ensure that the VSX facility is enabled by checking and setting the MSR.VSX bit. Be aware of potential exceptions such as NaNs or infinities, which can set flags in the FPSCR register. The operation respects the rounding mode specified in FPSCR.RN.