vpkshss

Vector Pack Signed Halfword Signed Saturate

vpkshss vD, vA, vB

Packs signed halfwords from two vector registers into a single vector register with signed saturation.

Details

The instruction concatenates the contents of VSR[VRA+32] and VSR[VRB+32], then for each integer value i from 0 to 15, it places the signed integer value in halfword element i of the concatenated source into byte element i of VSR[VRT+32] in signed integer format. If the value is greater than 2^7 - 1 or less than -2^7, it saturates and sets SAT to 1.

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
vsrc.qword[0] ← VSR[VRA+32]
vsrc.qword[1] ← VSR[VRB+32]
do i = 0 to 15
    VSR[VRT+32].byte[i] ← si8_CLAMP(EXTS(vsrc.hword[i]))
end

Programming Note

This instruction is useful for packing signed halfwords into bytes with saturation. Ensure that the source vectors are correctly aligned and that the vector facility (MSR.VEC) is enabled to avoid exceptions. Be aware of saturation conditions, as they will set the SAT bit in VSCR.

Example

vpkshss vd, va, vb

Encoding

Binary Layout
4
0
vD
6
vA
11
vB
16
462
 
Format VX-form
Opcode 0x100001CE
Extension VMX (AltiVec)
Registers Altered VSCR (SAT)

Operands

  • vD
    Target
  • vA
    Src A
  • vB
    Src B
  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register