bcdcfz.
Decimal Convert from Zoned
bcdcfz. vD, vB, PS
Converts BCD Zoned format to Signed Packed BCD.
Encoding
Binary Layout
4
0:5
VRT
6:10
6
11:15
VRB
16:20
1
21:29
PS
30
385
31
Operands
-
vD
Target -
vB
Source -
PS
Sign -
VRT
Target Vector Register -
VRB
Source Vector Register
Reference
View in PowerISA v3.1C Specification ↗
OPF Power ISA v3.1C
Description
The bcdcfz. instruction converts a zoned decimal value in VSR[VRB+32] to a packed decimal format and stores the result in VSR[VRT+32]. The conversion is based on the sign code and digit values of the source operand.
Operation
if MSR.VEC=0 then
Vector_Unavailable()
inv_flag ← ((VSR[VRB+32].byte[15].nibble[0] < 0xA) & (PS=1)) | (VSR[VRB+32].byte[15].nibble[1] > 0x9)
MIN ← (PS=0) ? 0x30 : 0xF0
MAX ← (PS=0) ? 0x39 : 0xF9
do i = 0 to 14
inv_flag ← inv_flag | (VSR[VRB+32].byte[i] < MIN) | (VSR[VRB+32].byte[i] > MAX)
end
if PS=0 then
src_sign ← VSR[VRB+32].nibble[30].bit[1]
else
src_sign ← (VSR[VRB+32].nibble[30] = 0b1011) | (VSR[VRB+32].nibble[30] = 0b1101)
eq_flag ← 1
do i = 0 to 14
result.nibble[i] ← 0x0
end
do i = 0 to 15
result.nibble[i+15] ← VSR[VRB+32].byte[i].nibble[1]
eq_flag ← eq_flag & (VSR[VRB+32].byte[i].nibble[1]=0x0)
end
lt_flag ← (eq_flag=0) & (src_sign=1)
gt_flag ← (eq_flag=0) & (src_sign=0)
result.nibble[31] ← (src_sign=0) ? 0xC : 0xD
CR.bit[56] ← inv_flag ? 0b0 : lt_flag
CR.bit[57] ← inv_flag ? 0b0 : gt_flag
CR.bit[58] ← inv_flag ? 0b0 : eq_flag
CR.bit[59] ← inv_flag
VSR[VRT+32] ← inv_flag ? undefined : result
Programming Note
The bcdcfz. instruction is used to convert zoned decimal values to packed decimal format. Ensure that the source vector register (VRB) contains valid zoned decimal data, as invalid input can lead to undefined results and set the CR6 flags accordingly. This instruction operates at the user privilege level and requires the Vector Facility to be enabled; otherwise, a Vector_Unavailable exception is raised.