bcdcfn.
Decimal Convert from National
bcdcfn. vD, vB, PS
Converts a national decimal value to packed decimal format and stores it in the target vector register.
Encoding
Binary Layout
4
0:5
VRT
6:10
7
11:15
VRB
16:20
1
21:29
PS
30
385
31
Operands
-
vD
Target -
vB
Source -
PS
Sign -
VRT
Target Vector Register -
VRB
Source Vector Register
Example
bcdcfn. vd, vb, 0
Registers Altered
CR6, VSR[VRT+32], VSR[VRB+32]Related
More in Vector BCD
Reference
View in PowerISA v3.1C Specification ↗
OPF Power ISA v3.1C
Description
The instruction checks if the source vector register contains a valid national decimal value. If valid, it converts it to packed decimal format and stores it in the target vector register. The condition register is updated based on the comparison of the source with zero.
Operation
if MSR.VEC=0 then
Vector_Unavailable()
src_sign ←(VSR[VRB+32].hword[7] = 0x002D)
eq_flag ←1
inv_flag ←(VSR[VRB+32].hword[7] != 0x002B) & (VSR[VRB+32].hword[7] != 0x002D)
do i = 0 to 6
eq_flag ←eq_flag & (VSR[VRB+32].hword[i] = 0x0030)
inv_flag ←inv_flag | (VSR[VRB+32].hword[i] < 0x0030) | (VSR[VRB+32].hword[i] > 0x0039)
end
lt_flag ←(eq_flag=0) & (src_sign=1)
gt_flag ←(eq_flag=0) & (src_sign=0)
do i = 0 to 23
result.nibble[i] ←0x0
end
do i = 0 to 6
result.nibble[i+24] ← VSR[VRB+32].hword[i].nibble[3]
end
result.nibble[31] ← (src_sign=0) ? ((PS=0) ? 0xC : 0xF) : 0xD
VSR[VRT+32] ←inv_flag ? undefined : result
CR.bit[56] ←inv_flag ? 0b0 : lt_flag
CR.bit[57] ←inv_flag ? 0b0 : gt_flag
CR.bit[58] ←inv_flag ? 0b0 : eq_flag
CR.bit[59] ←inv_flagProgramming Note
The bcdcfn. instruction is used to convert a national decimal value in a vector register to packed decimal format, updating the condition register based on comparison with zero. Ensure the source vector contains valid national decimal values; otherwise, the result is undefined and flags are set accordingly. This instruction requires the Vector Facility (MSR.VEC) enabled.