bpermd

Bit Permute Doubleword

bpermd RA, RS, RB

Permutes bits from RS based on the index values in RB. Highly optimized for bit shuffling.

Encoding

Binary Layout

31

0:5

RS

6:10

RA

11:15

RB

16:20

252

21:30

/

31

 

Format X-form

Opcode 0x7C0001F8

Extension Base

Operands

• RA
  Target Register
• RS
  Source Register (Data)
• RB
  Permute Control Byte Selects

Example

bpermd r3, r4, r5

// Complex bit permutation.

Related

More in Base

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Permutes the bits of RS according to bit indices specified in RB, placing the result in RA. Each byte of RB contains a 6-bit index (0-63) that selects which bit from RS to place at that bit position in RA. This is a Base-category scalar instruction with no CR or XER updates.

Operation

for i in 0 to 7 do; index ← RB[i*8+2:i*8+7]; if (index < 64) then RA[i] ← RS[index]; else RA[i] ← 0;

Programming Note

The fact that the permuted bit is 0 if the corresponding index value exceeds 63 permits the permuted bits to be selected from a 128-bit quantity, using a single index register.