bcdctz.

Decimal Convert to Zoned

bcdctz. vD, vB, PS

Converts Signed Packed BCD to Zoned format.

Encoding

Binary Layout

0:5

6:10

11:15

16:20

1217

21:31

Format VX-form

Opcode 0x10040581

Extension Vector BCD

Operands

vD
Target
vB
Source
PS
Sign
VRT
Target Vector Register
VRB
Source Vector Register

Example

bcdctz. vd, vb, 0

Registers Altered

CR6

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The contents of each nibble 0-30 must be a value in the range 0x0 to 0x9. Packed decimal values with sign codes of 0xA, 0xC, 0xE, or 0xF are interpreted as positive values. Packed decimal values with sign codes of 0xB or 0xD are interpreted as negative values.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
inv_flag ←(VSR[VRB+32].nibble[31] < 0xA)
do i = 0 to 30
    inv_flag ←inv_flag | (VSR[VRB+32].nibble[i] > 0x9)
ox_flag ←0
do i = 0 to 15
    ox_flag ←ox_flag | (VSR[VRB+32].nibble[i] != 0x0)
src_sign ←(VSR[VRB+32].nibble[31] = 0xB) | (VSR[VRB+32].nibble[31] = 0xD)
eq_flag ←(VSR[VRB+32].nibble[0:30] = 0)
lt_flag ←(eq_flag=0) & (src_sign=1)
gt_flag ←(eq_flag=0) & (src_sign=0)
do i = 0 to 14
    result.byte[i].nibble[0] ←(PS=0) ? 0x3 : 0xF
    result.byte[i].nibble[1] ←VSR[VRB+32].nibble[i+15]
end
if src.sign=0 then
    result.byte[15].nibble[0] ←(PS=0) ? 0x3 : 0xC
else
    result.byte[15].nibble[0] ←(PS=0) ? 0x7 : 0xD
end
result.byte[15].nibble[1] ←VSR[VRB+32].nibble[30]
VSR[VRT+32] ←inv_flag ? undefined : result
CR.bit[56] ←inv_flag ? 0b0 : lt_flag
CR.bit[57] ←inv_flag ? 0b0 : gt_flag
CR.bit[58] ←inv_flag ? 0b0 : eq_flag
CR.bit[59] ←inv_flag | ox_flag

Programming Note

The bcdctz. instruction converts packed decimal values to zoned format, interpreting sign codes and handling invalid nibble values. Ensure that the input data is correctly formatted with valid nibbles (0x0-0x9) and appropriate sign codes. The instruction operates on vector registers and requires the Vector Facility to be enabled; otherwise, it raises a Vector Unavailable exception. Check the condition register bits for flags indicating invalid input, less than, greater than, or equal conditions.