vexpandhm

Vector Expand Halfword Mask

vexpandhm vD, vB

Expands bits from a GPR mask into a halfword-element vector.

Encoding

Binary Layout

4

0:5

vD

6:10

0

11:15

vB

16:20

1666

21:31

 

Format VX-form

Opcode 0x10010642

Extension VMX (AltiVec)

Operands

• vD
  Target
• vB
  Source

Example

vexpandhm vd, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Expands individual bits from a source vector register into halfword-sized elements in the destination vector register, where each bit controls whether the corresponding halfword is set to all 1s or all 0s. This is a VMX instruction with no effect on condition registers or status fields.

Operation

for i in 0 to 7 do
  if vB[i] = 1 then
    vD[i*16:(i+1)*16-1] ← 0xFFFF
  else
    vD[i*16:(i+1)*16-1] ← 0x0000
  end if
end for

Programming Note

The vexpandhm instruction is useful for creating masks based on the least significant bit of each halfword in the source vector. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1 before using this instruction, as attempting to execute it with VEC=0 will result in a Vector Unavailable exception. This instruction operates on 8 halfwords per vector register and does not require any specific alignment of the data.