vexpandhm

Vector Expand Halfword Mask

vexpandhm vD, vB

Expands bits from a GPR mask into a halfword-element vector.

Details

The Vector Expand Halfword Mask instruction (vexpandhm) replicates the contents of bit 0 of each halfword element in the source VSR to all bits in the corresponding halfword element in the target VSR. If bit 0 is set, the target halfword is filled with all 1s; otherwise, it is filled with all 0s.

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 7
   if VSR[VRB+32].hword[i].bit[0]=1 then
      VSR[VRT+32].hword[i] ←0xFFFF
   else
      VSR[VRT+32].hword[i] ←0x0000
end

Programming Note

The vexpandhm instruction is useful for creating masks based on the least significant bit of each halfword in the source vector. Ensure that the Vector Facility (VEC) bit in the Machine State Register (MSR) is set to 1 before using this instruction, as attempting to execute it with VEC=0 will result in a Vector Unavailable exception. This instruction operates on 8 halfwords per vector register and does not require any specific alignment of the data.

Example

vexpandhm vd, vb

Encoding

Binary Layout

1666

Format VX-form

Opcode 0x10000682

Extension VMX (AltiVec)

Registers Altered MSR

Operands

vD
Target
vB
Source