vupkhsb

Vector Unpack High Signed Byte

vupkhsb vD, vB

Unpacks the high signed byte from each element of a vector register into halfwords of another vector register.

Encoding

Binary Layout

0

0:5

VRT

6:10

VRB

11:15

18

16:20

LI

21:29

AA

30

LK

31

 

Format VX-form

Opcode 0x1000020E

Extension VMX (AltiVec)

Operands

• vD
  Target
• vB
  Source
• VRT
  Target Vector Register
• VRB
  Source Vector Register

Example

vupkhsb vd, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

For vupkhsb, the signed integer value in byte element i of VSR[VRB+32] is sign-extended and placed into half-word element i in VSR[VRT+32].

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 7
    VSR[VRT+32].hword[i] ←EXTS16(VSR[VRB+32].byte[i])
end

Programming Note

This instruction is used to unpack the high signed bytes from one vector register into half-words of another. Ensure that the Vector Facility (MSR.VEC) is enabled; otherwise, a Vector Unavailable exception will be raised. The operation processes each byte element, sign-extending it to a half-word, which can affect the result if the original byte values are negative.