vupklpx

Pseudocode Operation

if MSR.VEC=0 then Vector_Unavailable()
do i = 0 to 3
   src ←VSR[VRB+32].hword[i+4]
   VSR[VRT+32].word[i].byte[0] ←EXTS8(src.bit[0])
   VSR[VRT+32].word[i].byte[1] ←EXTZ8(src.bit[1:5])
   VSR[VRT+32].word[i].byte[2] ←EXTZ8(src.bit[6:10])
   VSR[VRT+32].word[i].byte[3] ←EXTZ8(src.bit[11:15])
end

Programming Note

The vupklpx instruction is used to unpack the low halfwords of a vector register into bytes, sign-extending the first bit and zero-extending the remaining bits. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 128-bit vector registers and processes each halfword in the source register to produce four bytes per iteration.

Example