vupklpx

Vector Unpack Low Pixel

vupklpx vD, vB

Unpacks low 4 pixels to 4 words.

Encoding

Binary Layout

4

0:5

vD

6:10

0

11:15

vB

16:20

974

21:31

 

Format VX-form

Opcode 0x100003CE

Extension VMX (AltiVec)

Operands

• vD
  Target
• vB
  Source

Example

vupklpx vd, vb

Registers Altered

MSR

Related

More in VMX (AltiVec)

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Unpacks the four low-order pixel values (each 8 bits) from vB into four 32-bit word elements in vD, expanding each pixel into a word with implicit format expansion. This VMX/AltiVec instruction is commonly used in graphics processing and does not affect status registers.

Operation

for i in 0 to 3:
  pixel ← vB[8*i:8*i+7]
  vD[32*i:32*i+31] ← ExpandPixel(pixel)

Programming Note

The vupklpx instruction is used to unpack the low halfwords of a vector register into bytes, sign-extending the first bit and zero-extending the remaining bits. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will be raised. This instruction operates on 128-bit vector registers and processes each halfword in the source register to produce four bytes per iteration.