vsumsws

Vector Sum-across Signed Word Saturate

vsumsws vD, vA, vB

Adds the contents of four word elements of one vector register to a single word element of another vector register and saturates the result.

Encoding

Binary Layout

000100

0:5

6:10

11:15

16:20

11110

21:25

001000

26:31

Format VA-form

Opcode 0x10000788

Extension VMX (AltiVec)

Operands

vD
Target
vA
Src A
vB
Accumulator
VRT
Target Vector Register
VRA
Source Vector Register
VRB
Source Vector Register
VA
Source Vector Register
VB
Source Vector Register
VC
Source Vector Register

Example

vsumsws vd, va, vb

Registers Altered

VSCR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

The sum of the signed integer values in the four word elements of VSR[VRA+32] is added to the signed integer value in the word element 3 of VSR[VRB+32]. The low-order 32 bits of the result are placed into word element 3 of VSR[VRT+32], and the high-order 96 bits are set to zero. If the intermediate result is greater than 2^31 - 1, it saturates to 2^31 - 1; if less than -2^31, it saturates to -2^31.

Operation

if MSR.VEC=0 then
    Vector_Unavailable()
temp ←EXTS(VSR[VRB+32].word[3])
do i = 0 to 3
    temp ←temp + EXTS(VSR[VRA+32].word[i])
end
VSR[VRT+32].word[0] ←0x0000_0000
VSR[VRT+32].word[1] ←0x0000_0000
VSR[VRT+32].word[2] ←0x0000_0000
VSR[VRT+32].word[3] ←si32_CLAMP(temp)
VSCR.SAT ←sat_flag

Programming Note

This instruction is useful for accumulating sums of signed integers with saturation, preventing overflow. Ensure that the vector registers are properly aligned and that the VEC bit in the MSR is set to 1. Be aware of the saturation behavior; if the sum exceeds the 32-bit signed integer range, it will be clamped to the maximum or minimum value. The result is stored only in the fourth word element of the destination register, with the other elements zeroed out.