vmsumuhs

Vector Multiply-Sum Unsigned Halfword Saturate

vmsumuhs VRT,VRA,VRB,VRC

Performs a vector multiply-sum operation on unsigned halfwords and saturates the result.

Encoding

Binary Layout

0:5

VRT

6:10

VRA

11:15

VRB

16:20

VRC

21:31

Format VA-form

Opcode 0x10000027

Extension VMX (AltiVec)

Operands

VRT
Destination Vector Register
VRA
Source Vector Register A
VRB
Source Vector Register B
VRC
Source Vector Register C

Example

vmsumuhs v1, v2, v3, v4

Registers Altered

VSCR

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Computes the sum of products of unsigned halfword elements from VRA and VRB, adds the result to the corresponding word element in VRC, and saturates the final result to unsigned 32-bit range. This instruction requires VMX support and no condition flags are affected.

Operation

for i in 0 to 3 do
  product0 ← (u16)VRA[i*32:(i*32+15)] * (u16)VRB[i*32:(i*32+15)]
  product1 ← (u16)VRA[i*32+16:(i*32+31)] * (u16)VRB[i*32+16:(i*32+31)]
  sum ← product0 + product1 + (u32)VRC[i*32:(i*32+31)]
  VRT[i*32:(i*32+31)] ← Saturate_U32(sum)
end for

Programming Note

The vmsumuhs instruction is commonly used for performing vectorized multiply-sum operations on unsigned halfwords, which can be particularly useful in graphics and signal processing applications. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will occur. The operation saturates results to prevent overflow, setting the VSCR.SAT flag if saturation occurs. This instruction operates on 128-bit vectors, so ensure proper alignment of vector registers for optimal performance.