vmsumuhs

Vector Multiply-Sum Unsigned Halfword Saturate

vmsumuhs VRT,VRA,VRB,VRC

Performs a vector multiply-sum operation on unsigned halfwords and saturates the result.

Details

The vmsumuhs instruction performs a vector multiply-sum operation on unsigned halfwords. It multiplies each pair of corresponding halfwords from two source vectors, sums the results with an intermediate value from a third vector, and stores the saturated result in a destination vector.

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()

do i = 0 to 3
    temp ←EXTZ(VSR[VRC+32].word[i])
    do j = 0 to 1
        src1 ←EXTZ(VSR[VRA+32].word[i].hword[j])
        src2 ←EXTZ(VSR[VRB+32].word[i].hword[j])
        temp ←temp + src1 × src2
    end
    VSR[VRT+32].word[i] ←ui32_CLAMP(temp)
    VSCR.SAT ←sat_flag
end

Programming Note

The vmsumuhs instruction is commonly used for performing vectorized multiply-sum operations on unsigned halfwords, which can be particularly useful in graphics and signal processing applications. Ensure that the Vector Facility (MSR.VEC) is enabled before using this instruction; otherwise, a Vector_Unavailable exception will occur. The operation saturates results to prevent overflow, setting the VSCR.SAT flag if saturation occurs. This instruction operates on 128-bit vectors, so ensure proper alignment of vector registers for optimal performance.

Example

vmsumuhs v1, v2, v3, v4

Encoding

Binary Layout
4
0
VRT
6
VRA
11
VRB
16
VRC
21
 
Format VA-form
Opcode 0x10000028
Extension VMX (AltiVec)
Registers Altered VSCR

Operands

  • VRT
    Destination Vector Register
  • VRA
    Source Vector Register A
  • VRB
    Source Vector Register B
  • VRC
    Source Vector Register C