vdivesw

Vector Divide Extended Signed Word

vdivesw VRT,VRA,VRB

Divides the contents of two vector registers and updates the result in another vector register.

Details

For vdivesw, each word element of VSR[VRA+32] is treated as a signed integer, shifted left by 32 bits, and divided by the corresponding word element of VSR[VRB+32], which is also treated as a signed integer. The quotient is placed into the corresponding word element of VSR[VRT+32].

Pseudocode Operation

if MSR.VEC=0 then
    Vector_Unavailable()
do i = 0 to 3
    dividend ←EXTS(VSR[VRA+32].word[i]) << 32
    divisor  ←EXTS(VSR[VRB+32].word[i])
    VSR[VRT+32].word[i] ←CHOP32(dividend ÷ divisor)
end

Programming Note

The vdivesw instruction performs a signed division on each word element of the input vectors, shifting the dividend left by 32 bits before dividing. Ensure that the vector facility is enabled (MSR.VEC=1) to avoid exceptions. Be cautious of division by zero, which may result in undefined behavior or exceptions. The operation is performed at the user privilege level unless otherwise specified.

Example

vdivesw v1, v2, v3

Encoding

Binary Layout
4
0
VRT
6
VRA
11
VRB
16
 
Format VX-form
Opcode 0x1000038B
Extension VMX (AltiVec)
Registers Altered None

Operands

  • VRT
    Target Vector Register
  • VRA
    Source Vector Register
  • VRB
    Source Vector Register