lhz

Load Halfword and Zero

lhz RT, D(RA)

Loads a halfword (16 bits) from memory and clears the upper 48 bits.

Encoding

Binary Layout

0:5

6:10

11:15

16:31

Format D-form

Opcode 0xA0000000

Extension Base

Operands

RT
Target Register
D
Displacement
RA
Base Register

Example

lhz r3, 0(r4)

// Load unsigned 16-bit value.

Reference

View in PowerISA v3.1C Specification ↗ OPF Power ISA v3.1C

Description

Loads a 16-bit halfword from memory at address (RA + sign_extend(D)) and places it into RT with the upper 48 bits cleared to zero. The base register may be R0 if RA is zero in the instruction, in which case the displacement is used as an absolute address. No condition or status registers are affected.

Operation

if RA = 0 then
  EA ← sign_extend(D)
else
  EA ← (RA) + sign_extend(D)
RT ← (0 || [EA+1:EA])
// Load halfword at EA, zero-extend to 64 bits

Programming Note

The lhz instruction is commonly used for loading halfword values from memory into a register while ensuring the upper 16 bits are zeroed. Ensure that the effective address (EA) is properly aligned to avoid unaligned access exceptions. This instruction operates at user privilege level and will raise an exception if the EA is invalid or if there's a protection fault.

lhz